MF115200 - SEMI MF1152 - Test Method for Dimensions of Notches on Silicon Wafers Revision:SEMI MF1152-02 - Superseded including near-edge substrate contamination levels

including near-edge substrate contamination levels

This mandates test methods of organic compounds on wafer surfaces

SECS-II messages can be transmitted to and from and equipment using either the protocol defined in SEMI E4

SEMI E84-0304 (technical revision)

SEMI E6-92 (technical revision)

MF115200 - SEMI MF1152 - Test Method for Dimensions of Notches on Silicon Wafers Revision:SEMI MF1152-02 - Superseded including near-edge substrate contamination levelsWafers must be accurately aligned in various processing equipment during integrated circuit manufacture. A notch ground into the edge of the wafer at a specified orientation provides a positive method for such alignment. The accuracy of the critical dimensions of the notch controls the possible accuracy of the alignment. This Test Method may be used for process control, quality control, and incoming or outgoing inspection. Until an index of precision